module com_interface(
	input  wire clk_48, //external clock (48 MHz)
	input  wire rst_, //reset signal
	input wire rd,
	input  wire dtr,
	output wire dsr,
	output wire cd,
	input  wire rts,
	output wire cts,
	output wire clk2,
	output wire [15:0] q,
	output wire [15:0] data,
	output wire [10:0] addr,
	output wire [7:0] buffer
);

wire resout;
wire wren, tx;
hyperterm hyp(
    .clk_48(clk_48),
    .rst_(rst_),
    .tx(tx),
    .rd(rd),
    .dtr(dtr),
    .dsr(dsr),
    .cd(cd),
    .rts(rts),
    .cts(cts),
    .data(data),
    .addr(addr),
    .wren(wren),
    .clk2(clk2),
    .resout(resout),
    .buffer(buffer)
 );
 ram_2048x16_1p RAM (
    .address(addr),
    .clock(clk_48),
    .data(data),
    .wren(wren),
    .q(q)
  );

endmodule